1. Field
Example embodiments relate to a field effect transistor, and a method of manufacturing the same. Other example embodiments relate to a fin field effect transistor (FinFET), and a method of manufacturing the FinFET.
2. Description of the Related Art
In order to provide semiconductor devices with a more rapid operational speed and increased integration degree, a channel length of a MOS field effect transistor (MOSFET) has been gradually reduced. However, in a planar MOSFET, an electrical field may affect the planar MOSFET by a drain voltage because the channel length may become shorter. Further, this may cause a short channel effect where a channel drive capacity may be deteriorated due to a gate electrode. To control a threshold voltage of the planar MOSFET, increasing an impurity concentration of a channel may be required. However, this may cause relatively low mobility of carriers and a relatively low current drive force. Therefore, in the planar MOSFET, suppressing the short channel effect may be difficult because the planar MOSFET may have a more rapid operational speed and an increased integration degree.
A type of transistors, which have a structure capable of reducing the short channel effect, may include a fin field effect transistor (FinFET). The FinFET may include an active region having a three-dimensional fin shape. The fin may be surrounded by a gate electrode. Thus, a three-dimensional channel may be formed along a surface of the fin. Because the channel is formed on an upper surface and sidewalls of the fin, the FinFET may have a larger effect channel width in a relatively small horizontal area. Thus, a semiconductor device having the FinFET may have a relatively small size and a more rapid operational speed. Further, the short channel effect may be reduced owing to a reduced capacitance of the drain region. In order to improve operational characteristics of the FinFET, uniformly forming source/drain regions on a surface of the three-dimensional fin may be necessary. However, because a body width of the fin is gradually narrowed and the fin has the three-dimensional shape, the surface of the fin may not be readily doped with impurities.
Further, the FinFET may have a gate induced drain leakage (GIDL) current higher than that of the planar MOSFET. This may be caused by the three-dimensional shape of the fin that may provide a relatively large overlapped area between the gate electrode and the drain region. To decrease the GIDL current, minimizing or reducing the overlapped area between the source/drain regions and the gate electrode may be required. However, a process for forming the source/drain regions may include doping impurities, and activating the impurities by a thermal treatment. The thermal treatment may cause a horizontal and vertical diffusion of the impurities. The diffusion of the impurities may cause a continuous increase of the overlapped area between the source/drain regions and the gate electrode. As a result, the GIDL current may not be sufficiently reduced.
In a conventional method of reducing the GIDL current, after forming the gate electrode, an offset spacer may be formed on a sidewall of the gate electrode to reduce the overlapped area between the source/drain regions and the gate electrode. However, the offset spacer may be formed on a sidewall of the fin to be doped with the impurities as well as the sidewall of the gate electrode. Thus, the impurities in the sidewall of the fin, where the offset spacer is formed, may be different from those in the upper surface of the fin where the offset spacer may not be formed. Further, a higher energy to dope the sidewall of the fin with the impurities through the offset spacer may be required which causes damages to the surface of the fin.